Re: DSN capability with XDMA Subsystem core

Дата публикации: 26-02-2020 17:02:39

Hi,
is there any new development for the mentioned usecase? I've tried also to pull the cfg_dsn signal out but ran into the same issues with the generated stub files as mentioned before. They seem not to generate the cfg_dsn port although I added the port as good as I could to every verilog or VHDL file (*_core_top.sv, *_sim_netlist.v, *_sim_netlist_vhdl, *_stub.v, *_stub.vhdl). Vivado still throws an error, that no cfg_dsn port is defined. Is there a quick workaround, or is the information embedded in the encoded xdma_v3_0_vl_rfs.sv file?

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