Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified Database (UDB) as the source of truth for extension definition and a Large Language Model (LLM) connected through Model Context Protocol (MCP) tools to accelerate migration into compliant custom opcode space. In Phase 1, the agent inspects instruction encodings, identifies conflicts against ratified and reserved space, and proposes remappings for human approval. In Phase 2, it generates hardware and software artifacts from the approved mapping and validates them through automated build-and-test loops. To evaluate the flow, we are open-sourcing two packed-SIMD extensions and the supporting hardware and software, including a full-system simulator, GNU assembler support, Zephyr runtime support and even the RTL design for the more than 140 migrated instructions. The result is a working open-source end-to-end stack, from decoder to application code, demonstrating AI assistance as a practical aid for ISA architects and as an automation layer for the associated hardware and software engineering