When D-Wave bought Quantum Circuits for $550 million in the early days of this year, it marked a significant step in its plans to become a dual-platform player in quantum computing, matching its well-established annealing business with its in-development superconducting initiative. What made the acquisition so important was Quantum Circuits’ dual-rail qubit technologies and error-correction capabilities.

At the time, Quantum Circuits co-founder and chief scientist Rob Schoelkopf – who now fills the same role at D-Wave – said in that “fault-tolerant error-corrected quantum computing is within our reach, and this acquisition is expected to significantly speed up the timeline. We believe that no other company has a more powerful qubit with built-in error detection. Combining our dual-rail gate-model processor with D-Wave’s scalable control and readout is expected to enable a nearer-term path to large-scale error-corrected gate-model systems.”

Error correction continues to be a key hurdle that needs to be cleared for quantum computing to mature into a fault-tolerant, practical, and commercial business and significant strides have been made over the past several years. And as the advancements in the development of the technology continues to be made, the issue of error correction is not only about ensuring that quantum computing is useful, but also lowering the hardware costs by reducing the number qubits needed to detect and correct errors.

In a paper published in Nature this week, D-Wave detailed a hardware-based approach with a fast two-qubit entangling gate that the delivers high fidelity while retaining the error-correction capabilities of its superconducting dual-rail qubit design (the vendor’s dual-rail quantum processor is below) as the architecture scales. At its center is the ability to detect errors in hardware while preserving the error hierarchy in dual-rail environments.

Preserving the three-tier hierarchy is important. In dual-rail environments, the most common error is when an “erasure qubit” leaves its normal computational state. This triggers a known and detectable flag that signals which qubit failed and when the error happened, making it easier to detect and correct. Less common are phase flips, where the phase of the qubit is inverted – from positive to negative or vice versa – with bit flips (where the state of the qubit is changed from 0 to 1 or 1 to 0) being even rarer.

At the time the acquisition of Quantum Circuits was announced, Schoelkopf laid out the parameters of the error-correction research.

“The qubit is encoded by a single microwave photon that is shared between two superconducting cavities or resonators,” he said. “This gives us the usual abilities of quantum bits – a zero and a one and superpositions – but it also gives us a third state in which we can detect when the photon was lost. This means that this dual-rail qubit has error correction built in. It’s a unique functionality. What this means is that we can first use the dual-rail qubits themselves as physical qubits, use the error detection to obtain . . . the kind of fidelities that are usually associated only with [trapped ion] quantum computers, but with the speed a thousand times faster and the scalability of superconducting platforms.”

The top of this chart shows the schematic of a two dual-rail cavity qubit system, in which the control and target qubits are realized using pairs of three-dimensional λ/4 coaxial microwave cavities (red and blue). Three SQUID transmon couplers (grey and purple) each dispersively couple to pairs of cavity modes. These couplers are flux-pumped to actuate parametric beamsplitter interactions for single-qubit gates within the dual rails, and also to implement the dual-rail two-qubit gate, which is achieved by the middle coupler. Each cavity is coupled to an additional transmon qubit (green) and readout resonator (blue lines) that are used for SPAM. The middle of the chart above shows a diagram of the SWS gate sequence between two dual-rail cavity qubits. The bottom of the chart shows a schematic of photon population during the gate sequence for the four basis states. From Nature.

Error correction is done by pooling physical qubits into larger logical qubits. As systems scale, physical qubits create significant hardware demands, from dense control wiring and intense cooling needs to classical data-processing. Detecting particular errors in hardware should reduce the number of high-speed physical qubits.

Being able to detect particular errors in hardware should reduce the number of physical qubits needed for error correction, which will lessen the hardware overhead as quantum systems scale. According to D-Wave’s research, its two-qubit entangling gate enables this by reducing error rates while preserving the error hierarchy.

D-Wave’s results indicated the two-qubit gate runs with about 99.9 percent fidelity and with a gate time of about 500 nanoseconds. In addition, in simulations that were run, the vendor’s dual-rail architecture could reduce the logical error rate by 10X for each increment in error correction, which leads to the reduction in physical qubits needed.

“Our results present numerous opportunities for operating dual-rail cavity qubits at scale with high performance: from enabling high-circuit performance for short-depth circuits, to new types of error mitigation through flagging erasures, to – perhaps most excitingly – a viable path for implementing QEC using erasure qubits,” the D-Wave scientists wrote in the research paper. “All of these results highlight that superconducting dual-rail cavity qubits have quickly become an attractive path for achieving fault-tolerant quantum computing.”

D-Wave executives previewed some of these error-correction figures in June, when they unveiled an expanded roadmap for its dual-rail superconducting systems after folding Quantum Circuits into the company. Following the publishing of the research paper in Nature, they reiterated the role the error-correction architecture in ensuring the schedule, which includes a 49-physical-qubit system next year that will reduce the physical error rate 20-fold, and a 181-physical-qubit system the next year with a 2,000-fold error reduction factor, which they say will set the scalable blueprint for fault-tolerant architectures.

A 10-logical-qubit system that will support the first fault-tolerant algorithms will arrive in 2030, with a 100-logical-qubit quantum computer coming in 2032 that will be able to perform more than a million operations for initial quantum chemistry and quantum AI applications.

As noted earlier, D-Wave already has a growing business with its Advantage annealing quantum systems, which are used for complex optimization jobs and are accessible through its Leap cloud service as well as available for purchase. The vendor this week announced that bookings for the first six months this year reached $35.5 million, a 1,120 percent increase from the $2.9 million booked in the first half of 2025. Executives also reiterated their annealing quantum roadmap, which includes developing superconducting interconnects to scale the annealing architectures to multi-chip fabrics, a move that they expect will allow its upcoming Advantage3 system to eventually reach 20,000 qubits in 2029 and 100,000 qubits two years later.

A new I/O technology in the prototype stage now will allow D-Wave to scale its quantum chip to fit into a 100,000-qubit system while increasing the number of I/O lines by no more than 20 percent over the that needed for its current 4,500-qubit Advantage2 computer.

D-Wave got a boost late last month when AT&T said it was expanding its use of the vendor’s quantum technology after it was able to cut the time needed to process a network optimization job from about an hour to 15 seconds.

In-depth coverage of high end computing