With the AI race in full swing, big tech is constantly on the lookout to make custom chips that are able to compete with or offer alternatives to NVIDIA's pricey and short-in-supply GPUs. Google's Tensor Processing Units (TPUs) and Amazon's Trainium chips are among several that rely on less power consumption and costs to augment NVIDIA's products in AI computing. Now, a report from Morgan Stanley claims that Google's new TPU chips will be tailored to its Gemini models and eliminate the need for TSMC's chip-on-wafer-on-substrate (CoWoS) chip packaging technology.

Google's choice of packaging technologies for its TPU chips is a constant source of media speculation. Multiple reports have claimed that Google and its TPU design partner MediaTek might rely on Intel's EMIB-T packaging technology for the TPU chips. However, analysts have speculated that the choice might depend on yield, or Intel's ability to deliver workable chips.

Now, a report from Morgan Stanley claims that Google is interested in removing the need for packaging altogether on its chips. Intel's EMIB-T technology is widely believed to be suitable for medium-tier AI chips, with TSMC's CoWoS packaging being the preferred choice for high-performance chips such as NVIDIA's AI GPUs.

According to the details, Google is designing a chip called the 'Frozen V2' through which it aims to hit two birds with one stone, proverbially speaking. Through this TPU, the firm aims to create a chip that is customized specifically to run its Gemini AI models. Google aims to achieve customization through hardwiring the chips' SRAM on its silicon to remove the need for separate packaging technologies such as CoWoS.

Morgan Stanley adds that Frozen V2 can enter early-stage production next year and ramp production in 2028. As for Google's partners, it outlines that Marvell could be one choice; however, no details about the partners have been confirmed as of now. This approach isn't absolutely novel, as a similar one was unveiled by AI chip maker Taalas earlier this year.

Taalas also hardwires the neural network weights directly onto the silicon to remove the memory-compute data transfer bottleneck. However, the approach also comes with a key caveat of having to design a new chip each time a new AI model with significant upgrades over its predecessor is introduced. New chips then require fabricators, such as TSMC, to adjust their machinery for each production run.

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